CS501 Assignment 2 Solution and Discussion


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    Assignment No. 02
    Semester: Fall 2019
    Advance Computer Architecture – CS501
    Total Marks: 20

    Due Date: 28-11-2019
    Please carefully read the following instructions before attempting assignment
    OBJECTIVE OF ASSIGNMENT
    Objective of this assignment is to increase the learning capabilities of the students about:
    • Encoding of Assembly Instructions
    • Behavioral RTL description of instruction
    • ISA of Modified EAGLE
    • Address Bus and Data Bus in Modified EAGLE

    RULES FOR ASSIGNMENT
    It should be clear that your assignment will get credit only if:
    • The assignment is submitted before or on the due date.
    • The submitted assignment file is not corrupted or damaged.
    • The assignment is not copied (from another student or internet).

    UPLOADING INSTRUCTIONS
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    • Upload/Submit assignment in your VULMS assignment interface.
    • No assignment will be accepted through email.
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    NOTE
    No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence, refrain from uploading assignment in the last hour of deadline. It is recommended to upload solution file at least two days before its closing date.

    If you find any mistake or confusion in assignment (Question statement), please consult with your instructor before the deadline. After the deadline, no queries will be entertained in this regard. Moreover, keep checking announcements section.

    For any query, feel free to email at:
    [email protected]

    Best of Luck
    Question # 01 10 Marks
    Consider the below given table consisting of assembly instructions belonging to different processors.

    Instruction Processor Hexadecimal Code Behavioral RTL
    JPL R5, [26] Falcon - A
    STS R7, R2 (100) Falcon - E
    STACC R4, 36 Modified EAGLE
    DIV R2 EAGLE
    SHIFTL R5, R2, 7 FALCON - A

    Write machine code (in the hexadecimal representation) and behavioral RTL description for each instruction given in table.
    Question # 02 10 Marks
    Consider the below given tables belonging to Modified EAGLE architecture.
    • Table 1 shows the contents of registers R1, R2 and memory labels A, B, C. The contents of memory labels are memory addresses.

    Register Contents Memory Label Address
    R1 0015h A AB10h
    R2 25CBh B 3320h
    C AB0Eh

    Table 1: Contents in Registers and Memory labels
    • Table 2 represents byte- aligned memory map and shows the value stored at each memory address.

    Memory Address Memory Contents Memory Address Memory Contents
    AB0Eh 15h 3320h CEh
    AB0Fh 20h 3321h 55h
    AB10h 56h 3322h 39h
    AB11h EFh 3323h 20h

    Table 2: Contents at different memory addresses
    • Table 3 contains the instructions of an assembly program for Modified EAGLE. You are required to complete Table 3 by writing the values of destination operand, 16-bit address bus and 16-bit data bus after each instruction is executed.
    Write the complete steps for calculating the values of Destination Operand, Data Bus & Address Bus after the execution of each instruction.

    Instruction Contents stored in Destination Operand Data Bus Address Bus Calculation Steps
    LDACC B
    SUB R1
    LDACC C
    ADD R2
    STACC A

    Table 3: Data Bus and Address Bus Contents for Modified Eagle


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  • Cyberian's Gold

    @Ahsan-Waheed said in CS501 Assignment 2 Solution and Discussion:

    @zareen This is not a right assignment solution

    this is not a solution just idea how to solve the question.

    f85aff3a-865b-4bc6-b7a7-6fe281c2e3ac-image.png
    ceb1695a-5822-4980-8e8c-a3b4e94fa4cd-image.png


  • Cyberian's Gold

    @Ahsan-Waheed said in CS501 Assignment 2 Solution and Discussion:

    @zareen This is not a right assignment solution

    this is not a solution just idea how to solve the question.



  • @zareen This is not a right assignment solution


  • Cyberian's Gold

    jump instruction
    b7008c25-f048-46f3-9b8c-c0bca40c0ba8-image.png


  • Cyberian's Gold

    Control Instruction
    5c133d07-ce7b-4c97-a9d4-70dc4adfbba5-image.png


  • Cyberian's Gold

    We have looked at the various jump instructions in our study of the FALCON-A. Using that knowledge, this problem can be solved easily.
    0ef8e85e-982c-4123-a722-38ba048256a6-image.png


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    Solution
    Addressing modes relate to the way architectures specify the address of the objects they access. These objects may be constants and registers, in addition to memory locations.
    bfd20701-e200-4cc6-b14d-577fcb582667-image.png


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    Fields in the FALCON-A InstructionsWe now use the RTL naming operator to name the various fields of the RTL instructions.Naming the fields appropriately helps us make the study of the behavior of a processormore readable.op<4…0>:= IR<15…11>:operation code fieldra<2…0> := IR<10…8>:target register fieldrb<2…0> := IR<7…5>:operand or address indexrc<2…0> := IR<4…2>:second operandc1<4…0> := IR<4…0>:short displacement fieldc2<7…0> := IR<7…0>:long displacement or the immediate field


  • Cyberian's Gold

    A better method is to use the addi instruction with the constant set to 0.
    e4deab6a-7149-48ff-a6a0-03482bce61d9-image.png


  • Cyberian's Gold

    This instruction is to load a register from an input/output device. The effective address of the I/O device has to be calculated before it is accessed to read the word into the destination register ra, as shown in the example:in R5, R4(100)In RTL:R[5]←IO[R[4]+100]


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    ce783c86-e64f-4036-8a4d-0c97e30cb031-image.png


  • Cyberian's Gold

    We can also find the machine code for these instructions. The machine code (in the hexadecimal representation) is given for these instructions in the given table.
    541367a2-d798-4e68-b10c-646873903d63-image.png



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