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CS501 GDB 1 Solution and Discussion

CS501 - Advance Computer Architecture

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zareen Cyberian's Gold last edited by

Fixed length instructions vs Variable length instructions.

Fixed length instructions:-

All the records in the file are of same size.
Leads to memory wastage.
Access of the records is easier and faster.
Exact location of the records can be determined: location of ith record would be.n*(i-1), where n is the size of every record.

Variable length instructios:-

Different records in the file have different sizes.
Memory efficient.
Access of the records is slower.

Large cache blocks vs small cache blocks.

The “largest” block size case is best for repeated, in-order memory accesses (best for spacial locality) and worst for repeated, random memory accesses (worst for temporal locality).

The “smallest” block size case is worst for repeated, in-order memory accesses (worst for spacial locality) and best for repeated, random memory accesses (best for temporal locality). It is good for out-of-order memory accesses, depending on the size of the working set.

Simple instruction set vs complex instruction set.

Characteristic of Simple instruction set:

The simple instruction set provides commands to the processor, to tell it what it needs to do. The instruction set consists of addressing modes, instructions, native data types, registers, memory architecture, interrupt, and exception handling, and external I/O.

Characteristic of Complex instruction set:

Complex instruction, hence complex instruction decoding.
Instruction are larger than one word size.
Instruction may take more than single clock cycle to get executed.
Less number of general purpose register as operation get performed in memory itself.
Complex Addressing Modes.
More Data types.
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SOLVED CS501 Assignment 2 Solution and Discussion
CS501 - Advance Computer Architecture • cs501 assignment 2 solution discussion fall 2019 • • zareen

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Solution # 1
Instruction Processor Hexadecimal Code Behavioral RTL JPL R5, [26] Falcon - A 10000 101 00011010, 1000 0101 0001 1010, 851A (R[5] ≥ 0): PC ← PC+ (26-PC); STS R7, R2 (100) Falcon - E 00101 111 010, 000000000000001100100, 0010 1111 0100 0000, 0000 0000 0110 0100, 2F40 0064 M[R[2]+100] ← R [7] STACC R4, 36 Modified EAGLE 10111 100 00100100, 1011 1100 0010 0100, BC24 M[R[4] + ([email protected]<7>)©C] ← ACC C represents the constant 36 DIV R2 EAGLE 10000 010, 1000 0010, 82 R[0] ← R[0]/R[2] R[2] ← R[0]%R[2] SHIFTL R5, R2, 7 FALCON - A 01100 101 010 00111, 0110 0101 0100 0111, 6547 R[5]<15…0> ← R [2]<(15- N)…0>©([email protected]) N represents constant 7
Solution # 2
Instruction Value of Destination Operand Data Bus <15…0> Address Bus (15…0> LDACC B 55CEh 55CEh 3320h SUB R1 55B9h N/A N/A LDACC C 2015h 2015h AB0Eh ADD R2 45E0h N/A N/A STACC A 45E0h 45E0h AB10h
Table 3 Data Bus and Address Bus Contents for Modified Eagle

Calculation Steps (Instruction-By-Instruction)

• LDACC B
LDACC stands for load accumulator. In LDACC, the destination operand is accumulator and source operand is the memory location labelled as B. The memory label B points to the memory address 3320h. When this instruction is executed, the value stored at memory address 3320h will be read and loaded in Accumulator register. This address 3320h will be copied into Address Bus which will then read its contents from memory and load the contents at data bus. The operand size in Modified EAGLE is 2-byte. Therefore, the values stored at addresses 3320h and 3321h will be loaded at data bus. These values are CEh and 55h respectively. Since, Modified EAGLE employs Little endian notation hence, the 2-bye value will be read as 55CEh. The value of data bus will also be 55CEh and this will be loaded into destination operand Accumulator.
• SUB R1
SUB R1 means to subtract the value of source operand register R1 which is 0015h, from the destination operand Accumulator (ACC) register which contains 55CEh. The result of subtraction will be stored back into ACC. After subtraction, the value stored in ACC will be 55B9h. Because SUB is not a memory instruction, we are not concerned with the contents of Data Bus or Address Bus because the values we need to execute the instruction are already available in registers. Hence, Data Bus and Address Bus values will be labelled as N/A.
• LDACC C
When this instruction is executed, the value stored at memory address labelled with C is read and loaded in Accumulator register ACC. In this case, the address of the C is AB0Eh which is also the value of address bus. The operands in Modified EAGLE are 2-byte values. The contents at addresses AB0Eh and AB0Fh will be copied into data bus which will then be loaded into ACC register. These contents are 15h and 20h. Due to Little endian notation, the 2-bye value will be 2015h. The value of data bus will be 2015h and same will be loaded in destination register ACC.
• ADDR2
When ADD is executed, the value of register R2 is added to ACC register. Hence, after the execution, the ACC register will hold 45E0h. AS usual, ADD is not a memory instruction, so we are not concerned with the values of Data Bus and Address Bus and both are labelled as N/A.
• STACC A
STACC stands for Store ACC. There is one destination operand which is a memory label A. When the instruction is executed, the value of Accumulator register ACC is stored at the memory address labelled by A. The destination memory address will be AB10h. The value of ACC is 45E0h will be stored as address AB10h. However, due to Little-Endian notation, the address will be stored as E0h at memory location AB10h and then 45h at memory location AB11h.
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SOLVED CS501 Assignment 1 Solution and Discussion
CS501 - Advance Computer Architecture • cs501 assignment 1 solution discussion fall 2019 • • zareen

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Solution (A)
The formula to calculate the execution time : Execution Time = IC  CPI  T
IC for Load / Store Instructions
IC for ALU instructions
IC for Control instructions
= Total Instructions  Ratio of Load / Store Instructions = 200  0.35
= 70 instructions
= Total Instructions  Ratio of ALU Instructions = 200  0.55
= 110 instructions
= Total Instructions  Ratio of Control Instructions = 200  0.10
= 20 instructions
Now, we will calculate the total clock cycles required to execute each type of instructions
Total Clock Cycles for Load / Store
Total Clock Cycles for ALU
Total Clock Cycles for Control
= IC for Load / Store  CPI for Load / Store = 70  2.5
= 175 clock cycles
= IC for ALU  CPI for ALU = 110  1.25
= 137.5 clock cycles
= IC for control  CPI for control = 20  3
= 60 clock cycles
Time required (in seconds) for each clock cycle (T)=1/CPU frequency 1 / 500  106 = 0.002  10−6 seconds
= 210−9 seconds
Now finally, we will calculate the execution time
Execution Time (ET ) = Total Clock Cycles  1/ CPU Frequency
= (175 + 137.5 + 60)  (1/ 500  106 ) seconds
= 372.5210−9seconds 1/500106 =210−9seconds = 745  10−9 seconds
= 745 nanoseconds

Solution (B)
If decrease the average CPI for ALU by 20%, the new average CPI
New CPI for ALU = 1.25  (100−20)/100 = 1.25  0.8
= 1 CPI
If average CPI for Load / Store instruction is increased by 10%, new average CPI New CPI for Load / Store = 2.5  (100 +10)/100
= 2.5  1.1 = 2.75 CPI
Hence, new execution time will be
ExecutionTime(E.T) = (702.75+1101+203)x(1/500106)seconds
= (192.5+110+60)/(5108)seconds
= 362.5  2  10−9 seconds = 725  10−9 seconds
= 725 nanoseconds

Q. 2 Solution:

Solution A (0-Address Code)
PUSH B
PUSH C
ADD ; gives B+C PUSH A
MUL ; gives A(B+C) PUSH 2
PUSH A
MUL ; gives 2A PUSH C
MUL ; gives 2AC
PUSH B
DIV ; gives 2AC/B
SUB ; gives A(B+C) - 2AC/B
PUSH C
PUSH C
MUL ; gives C2
ADD ; gives POP D
A(B+C) - 2AC/B + C2

Solution A (1-Address Code)
LDA C MULA C STA X
LDA A MULA C MULA 2
; loads the value stored at memory location C in Accumulator ; gives C2
; stores C2 at memory location X
; loads the value stored at memory location A in Accumulator ; gives AC
; gives 2AC
DIVA B ADDA X STA Y
LDA B ADDA C MULA A SUB Y STA D
; gives 2AC/B
; adding 2AC/B with C2 stored in X gives 2AC/B + C2 ; stores 2AC/B + C2 at memory location Y
; loads the value stored at memory location B in Accumulator ; gives (B+C)
; gives A(B+C)
; subtracts 2AC/B + C2 from A(B+C)
; stores the result at memory location D

Fall 2019_CS501_1_SOL.pdf
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CS501 GDB 1 Solution and Discussion

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