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Re: CS302 GDB1 Solution and discussion
Total Marks 5
Starting Date Thursday, February 18, 2021
Closing Date Friday, February 19, 2021
Status Open
Question Title PAL vs PLA - Gaded Discussion Board (GDB)
Question DescriptionCS302 – Digital Logic Design
Graded Discussion Board
Suppose you had reduced a 32-variable Boolean expression using Quine–McCluskey algorithm to a 12-variable expression. For the generated simplified expression, you are required to implement it into a digital logic circuit. You can only use Programmable Array Logic (PAL) or Programmable Logic Array (PLA) devices.
Assume that we had selected a Programmable Array Logic (PAL) and a Programmable Logic Array (PLA) for you to choose between.
Using TICPAL22V10Z-25C (Programmable Array Logic)
Using PLUS173–10 (Programmable Logic Array).
Your selections among stated PLA and PAL must consider the following constraints:Complexity
Flexibility
Speed
Functionality
Cost
Important instructions for GDB submission:You must provide a precise and to the point answer. Your answer should be no more than 5 to 6 lines and do avoid irrelevant details.
Post your answer on the Graded Discussion Board (GDB), GDB through email or MDB will not be accepted in any case.
GDB will only be open for 48 hours, no more time or grace day will be provided.
Any answers copied from the internet or other student will get zero marks. -
Re: CS302 Assignment 2 Solution and Discussion
Digital Logic Design (CS302)
Assignment # 02Total marks = 20
Deadline Date
15/06/2020Please carefully read the following instructions before attempting assignment.
RULES FOR MARKING
It should be clear that your assignment would not get any credit if:
The assignment is submitted after the due date.
The submitted assignment does not open or file is corrupt.
Strict action will be taken if submitted solution is copied from any other student or from the internet.You should concern the recommended books to clarify your concepts as handouts are not sufficient.
You are supposed to submit your assignment in .doc or docx format.
Any other formats like scan images, PDF, zip, rar, ppt and bmp etc will not be accepted.Topic Covered:
• SOP to POS Conversion
• K-MapNOTE
No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence refrain from uploading assignment in the last hour of deadline. It is recommended to upload solution file at least two days before its closing date.
If you people find any mistake or confusion in assignment (Question statement), please consult with your instructor before the deadline. After the deadline no queries will be entertained in this regard.
For any query, feel free to email at:
[email protected]Questions No 01 Marks (10)
Map the given table on K-map. Make relevant pairs and find simplified SOP expression.
A B C D E Output
0 0 0 0 0 1
0 0 0 0 1 1
0 0 0 1 0 1
0 0 0 1 1 0
0 0 1 0 0 1
0 0 1 0 1 1
0 0 1 1 0 X
0 0 1 1 1 0
0 1 0 0 0 0
0 1 0 0 1 X
0 1 0 1 0 1
0 1 0 1 1 1
0 1 1 0 0 X
0 1 1 0 1 0
0 1 1 1 0 1
0 1 1 1 1 X
1 0 0 0 0 1
1 0 0 0 1 0
1 0 0 1 0 X
1 0 0 1 1 0
1 0 1 0 0 1
1 0 1 0 1 1
1 0 1 1 0 0
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 0 1 X
1 1 0 1 0 0
1 1 0 1 1 1
1 1 1 0 0 0
1 1 1 0 1 X
1 1 1 1 0 0
1 1 1 1 1 1Questions No 02 Marks (10)
Map the given canonical sum (SOP) on K-Map. Pair the terms of canonical product (POS) and find simplified POS expression.
Canonical Sum = ∑A, B, C, D (1, 2, 5, 6, 8, 10, 11, 13, 14, 15) -
Digital Logic Design (CS302)
Assignment # 01Total marks = 20
Deadline:01-06-2020
Please carefully read the following instructions before attempting assignment.
RULES FOR MARKING
It should be clear that your assignment would not get any credit if:
The assignment is submitted after the due date.
The submitted assignment does not open or file is corrupt.
Strict action will be taken if submitted solution is copied from any other student or from the internet.You should concern the recommended books to clarify your concepts as handouts are not sufficient.
You are supposed to submit your assignment in .doc or docx format.
Any other formats like scan images, PDF, zip, rar, ppt and bmp etc will not be accepted.Topic Covered:
Number Systems
Octal number
BCD Numbers
Lectures Covered
Lecture 01- 06NOTE
No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence refrain from uploading assignment in the last hour of deadline. It is recommended to upload solution file at least two days before its closing date.
If you people find any mistake or confusion in assignment (Question statement), please consult with your instructor before the deadline. After the deadline no queries will be entertained in this regard.
For any query, feel free to email at:
[email protected]Questions No 01 Marks (05)
Perform decimal to binary conversion on given decimal number using Sum-of-weights method. Verify the answer using repeated division method.
Decimal Number=1050
Questions No 02 Marks (10)
Perform the following arithmetic operations. For conversion you can use indirect method of conversion only.
〖(E2BC3F)〗_16-(10110101000000011110001)_2+ (537476217)_8 =(________)_16
Questions No 03 Marks (05)Perform BCD addition between these two numbers. Kindly perform all the steps.
46
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Digital Logic Design (CS302)
Assignment # 03Total marks = 20
Deadline Date
27/01/2020Please carefully read the following instructions before attempting assignment.
RULES FOR MARKING
It should be clear that your assignment would not get any credit if:
The assignment is submitted after the due date.
The submitted assignment does not open or file is corrupt.
Strict action will be taken if submitted solution is copied from any other student or from the internet.You should concern the recommended books to clarify your concepts as handouts are not sufficient.
You are supposed to submit your assignment in .doc or docx format.
Any other formats like scan images, PDF, zip, rar, ppt and bmp etc will not be accepted.Topic Covered:
• State Diagram
• Counters
• K-Maps
• Circuit DesignNOTE
No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence refrain from uploading assignment in the last hour of deadline. It is recommended to upload solution file at least two days before its closing date.
If you people find any mistake or confusion in assignment (Question statement), please consult with your instructor before the deadline. After the deadline no queries will be entertained in this regard.
For any query, feel free to email at:
[email protected]Questions No 01 Marks (20)
You are required to design a 4-bit even up-counter using D flip flop by converting combinational circuit to sequential circuit. The counter will only consider even inputs and the sequence of inputs will be 0-2-4-6-8-10-0.
Draw the State diagram. Generate State & Transition Table. Generate simplified Boolean Expression. Design the final Circuit diagram.
You are required to perform following tasks: -
Digital Logic Design (CS302)
Assignment # 02Total marks = 20
Deadline Date
27 Nov 2019Please carefully read the following instructions before attempting assignment.
RULES FOR MARKING
It should be clear that your assignment would not get any credit if:
The assignment is submitted after the due date.
The submitted assignment does not open or file is corrupt.
Strict action will be taken if submitted solution is copied from any other student or from the internet.You should consult the recommended books to clarify your concepts as handouts are not sufficient.
You are supposed to submit your assignment in .doc or docx format.
Any other formats like scan images, PDF, zip, rar, ppt and bmp etc will not be accepted.Topic Covered:
Expression Simplification
Quine-McCluskey Simplification MethodNOTE
No assignment will be accepted after the due date via email in any case (whether it is the case of load shedding or internet malfunctioning etc.). Hence refrain from uploading assignment in the last hour of deadline. It is recommended to upload solution file at least two days before its closing date.
If you people find any mistake or confusion in assignment (Question statement), please consult with your instructor before the deadline. After the deadline no queries will be entertained in this regard.
For any query, feel free to email at:
[email protected]Question Marks (20)
Consider the below given canonical sum:∑_(A,B,C,D,E)▒〖(2,4,6,8,10,12,14,16,18,20,22,24,26,28,30)〗
Write the SOP expression for the given sum. Find the prime implicants from given minterms using Quine-McCluskey simplification method. Extract the simplified expression.Note: Perform all steps of this method. In case of missing steps, marks will be deducted.
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In circuit designing industry, the focus is on transistor density, clock speed and power/performance ratio optimization. Due to the emergence of Dark Silicon issue, the focus has shifted entirely on power/performance ratio. Performance and power tradeoff is still the most crucial issue in the design of circuits. Suppose you are working on the design of a processor for a Radar System. Which one of the parameters (Performance or Power) will you consider being the most important in this situation?
Justify your answer with good reasons.
SOLVED CS302 GDB1 Solution and discussion
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In circuit designing industry, the focus is on transistor density, clock speed and power/performance ratio optimization. Due to the emergence of Dark Silicon issue, the focus has shifted entirely on power/performance ratio. Performance and power tradeoff is still the most crucial issue in the design of circuits. Suppose you are working on the design of a processor for a Radar System. Which one of the parameters (Performance or Power) will you consider being the most important in this situation?
Justify your answer with good reasons.
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The large energy cost of memory fetches limits the overallefficiency of applications no matter how efficient the ac-celerators are on the chip. As a result the most importantoptimization must be done at the algorithm level, to reduce off-chip memory accesses, to createDark Memory. The algorithmsmust first be (re)written for both locality and parallelism beforeyou tailor the hardware to accelerate them.Using Pareto curves in theenergy/opandmm2/(op/s)spaceallows one to quickly evaluate different accelerators, memorysystems, and even algorithms to understand the trade-offsbetween performance, power and die area. This analysis isa powerful way to optimize chips in the Dark Silicon era.
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