The large energy cost of memory fetches limits the overallefficiency of applications no matter how efficient the ac-celerators are on the chip. As a result the most importantoptimization must be done at the algorithm level, to reduce off-chip memory accesses, to createDark Memory. The algorithmsmust first be (re)written for both locality and parallelism beforeyou tailor the hardware to accelerate them.Using Pareto curves in theenergy/opandmm2/(op/s)spaceallows one to quickly evaluate different accelerators, memorysystems, and even algorithms to understand the trade-offsbetween performance, power and die area. This analysis isa powerful way to optimize chips in the Dark Silicon era.
UNSOLVED CS302 GDB1 Solution and discussion
Huzaifa Asif last edited by
Total Marks 5
Starting Date Thursday, February 18, 2021
Closing Date Friday, February 19, 2021
Question Title PAL vs PLA - Gaded Discussion Board (GDB)
CS302 – Digital Logic Design
Graded Discussion Board
Suppose you had reduced a 32-variable Boolean expression using Quine–McCluskey algorithm to a 12-variable expression. For the generated simplified expression, you are required to implement it into a digital logic circuit. You can only use Programmable Array Logic (PAL) or Programmable Logic Array (PLA) devices.
Assume that we had selected a Programmable Array Logic (PAL) and a Programmable Logic Array (PLA) for you to choose between.
Using TICPAL22V10Z-25C (Programmable Array Logic)
Using PLUS173–10 (Programmable Logic Array).
Your selections among stated PLA and PAL must consider the following constraints:
Important instructions for GDB submission:
You must provide a precise and to the point answer. Your answer should be no more than 5 to 6 lines and do avoid irrelevant details.
Post your answer on the Graded Discussion Board (GDB), GDB through email or MDB will not be accepted in any case.
GDB will only be open for 48 hours, no more time or grace day will be provided.
Any answers copied from the internet or other student will get zero marks.